Computer system and method that eliminates the need for an operating system

ABSTRACT

A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.11/626,248, filed Jan. 23, 2007, which is a continuation of Ser. No.10/444,768, filed May 22, 2003, which is a continuation of U.S.application Ser. No. 09/770,810, filed Jan. 26, 2001, each of which areincorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to computer architecture, hardware and method andin particular, to computer architecture, hardware and method thateliminates the need for an operating system.

2. Background of the Invention

FIG. 1 illustrates a conventional computer system architecture 100comprising a hardware platform layer 200, a firmware layer 300, anoperating system layer 400 and an application programs layer 102. Thehardware platform layer 200 is the physical layer of the computer systemthat performs the actual operations of the computer system. The firmwarelayer 300 performs, among others, the interface between the hardwareplatform layer 200 and the operating system layer 400. The operatingsystem layer 400 is a software layer that performs the management of thecomputer resources such as processor resource management, memoryallocation management, device resources management, and data filemanagement. The operating system is also the base upon which applicationprograms are built. The application programs layer 102 comprisescomputer programs that provide instruction sets that manipulate and/orprocess data in accordance with a desired result. Examples are wordprocessor, database, spread sheet and web browser programs.

FIG. 2 illustrates a conventional hardware platform layer (also commonlyreferred to as a “computer”) 200 of a computer system comprising acentral processing unit (CPU) 202, a read only memory (ROM) 204 and amain memory 206 coupled together through a system bus 208. Theillustrated configuration is representative of a bus architecture typecomputer system that is commonly used and includes Personal ComputerInterface (PCI), Industry Standard Architecture (ISA), Extended ISA(ESIA) and other bus standards. The computer 200 need not be limited toa bus architecture and may use a different architecture. The computer200 further comprises various controllers such as a memory controller212, a direct memory access (DMA) controller 214, an interruptcontroller 216, an input/output (I/O) controller 218, an integrateddrive electronics/floppy drive controller (IDE/FDC) controller 222 and avideo controller 224, among others. Various devices are coupled to thecontrollers so that the computer 200 can interact with a user or withthe outside world. For instance, a video monitor 226 is coupled to thevideo controller 224 to display various information, a keyboard 228 anda pointing device 232 is coupled to the I/O controller 218 via a serialport to input data and commands to the computer 200, a printer 234 isalso coupled to the I/O controller 218 via a parallel port to generatehard copies of data requested by the user. The IDE/FDC controller 222controls various disk drives such as a diskette drive 236, a hard-diskdrive 238, a compact disc (CD) ROM drive 242 and a digital video disc(DVD) ROM drive 244 and a modem 246 provides communication to theoutside world such as the Internet. Typically, the hardware has one ormore expansion slots 248 to receive various expansion cards that enhanceor add features of the hardware platform, thus a modem card 246 may beinserted into the expansion slot 248 to provide a communicationsfeature.

The firmware layer such as a Basic Input Output Operating System (BIOS)300 may be located in the ROM 204 and is generally specific to thehardware platform of the computer that it supports. The BIOS routinesinclude various setup procedures and Power On Self Test (POST). Thevarious setup procedures include the configuration of the variouscontrollers in which the BIOS acts as an uniform interface between thecontrollers and the operating system, thus allows the operating systemto access the hardware platform 200. The BIOS supports the interchangeof data that uses the various controllers, devices such as keyboard,mouse, video monitor, disk drives, printer and so forth. Other setupprocedures include preliminary memory setup for the operating system,fault handling, clock and timers for various circuits, for example, thedynamic random access memory (DRAM) refresh circuit that refreshes theDRAMs that comprise the main memory. The POST performs various self teston the memory and controllers and if a fault is found during the selftest, an error message in a form of an audio beep and/or an errormessage is displayed.

FIG. 3 is a flow chart of an exemplary power-up sequence using the BIOSthat may conform to Compaq Computer Corporation, Phoenix TechnologiesLtd. and Intel Corporation, Plug and Play BIOS Specification, Version1.0a, May 5, 1994, which is incorporated herein by reference. The BIOSmay also conform to Intel Corporation and Microsoft Corporation, Plugand Play ISA Specification, Version 1.0a, May 5, 1994, which isincorporated herein by reference. Plug & Play (PnP) specification allowsfor a computer operated configuration of devices attached to thecomputer without manual manipulation by a user. The user can add a newdevice, such as a sound card, and the computer will automatically detectthe device and provide a device driver to operate the card (which mayinclude requesting the user to insert a disk or a CD that contains thedevice driver if the computer does not already have the driverinternally). A PnP conforming device usually has the characteristics ofbeing able to uniquely identify itself; indicate the services itprovides and the resources it requires; identify the device driver thatsupports it; and an operating system to control the device. Thesefeatures are important to the operating system in that they allow theoperating system to establish a working configuration for all devicesconnected to the computer and to load appropriate device drivers intomemory.

Device drivers are software modules comprising logic for controlling thelow level or specific components of a device, thus allowing theoperating system to control the device. For example, a device driver maybe used for controlling a magnetic disk drive coupled to the computer.In this example, the device driver will control various hardwarespecific registers, latches, signals or other components of the magneticdisk drive device. A device driver is usually specifically configured tocommunicate with a particular device.

Referring now to FIG. 3, according to one power-up sequence, at stage302, the computer is powered on or a reset signal is received in whichthe computer forces the components within the computer includingaccessible devices to a reset logic state. At reset logic state, thecomputer does not “know” its actual configuration including what devicesincluding those on the expansion cards are attached to the computer.After a predefined period of time has passed in which the power supplyhas stabilized, at stage 304, the CPU starts at a starter address thatpoints to the ROM in which the BIOS is located. The POST routine of theBIOS is initiated and it tests the dynamic random access memories(DRAMS) that make up the main memory along with certain devices andcomponents of the system to determine their operability. During thetesting process, a copy of the BIOS is retrieved from the ROM and isshadowed into the main memory. The BIOS has a set of instructionroutines that prepares the computer system to receive the operatingsystem from an initial load device (IPL) which may be a disk drive. Atstage 306, the BIOS attempts turn off all the devices to determine whichdevices (i.e. IPLs) may be used to find and launch the operating system.IPLs are detected at this stage because IPLs cannot be turned off. Atstage 308, the BIOS turns on the devices and places non-IPLS in waitstate to be initialized by the operating system. At stage 310, the BIOSexecutes a bootstrap routine that causes the kernel of the operatingsystem (usually contained in the hard-disk drive) to load into the mainmemory. At this stage, the hardware control by the firmware (i.e., theBIOS) is passed to the software (which is the kernel). The kernel 402provides the core function of the operating system which is computerresource management such as process execution, memory management,dynamic linked library management, scheduling, file system management,I/O services and user interface presentation, among others.

At stage 312, the kernel initiates an isolation procedure that isolatesthe devices individually. The key to the isolation protocol is that eachdevice contains a unique 72-bit number known as a serial identifier.Once a device is isolated, it is assigned a Card Serial number (CSN)that is unique to the assigned device and serves as a “handle” in whichthe operating system identifies the device and with which the deviceidentifies itself, for instance when generating an interrupt. At stage314, the kernel reads the isolated devices individually for resourcerequirements of the device. The resources required by the devicesinclude DMA, interrupt request (IRQs), I/O and memory addresses. Atstage 316, the kernel creates a comprehensive list of the resourcerequirements of each device. At stage 318, because the kernel knows theavailable system resources, the kernel allocates the available resourcesto the devices as needed while ensuring the resource allocation isnon-conflicting. At stage 320, as the kernel allocates system resourcesto the devices an allocation map is created and stored in memory. Inaddition to the creation of the allocation map, At stage 322, using theidentification number provided by the device, the kernel identifies theassociated device driver that is usually stored in the hard-disk drive.Should the device driver be unavailable, the kernel will prompt the userto provide the device driver. All device drivers associated with thedetected devices are loaded into the main memory which is used by thekernel to control the devices. Further details of the power-up sequencesmay be found in Plug and Play ISA Specification. The isolation,interrogation of the various devices and loading of the device driversinto the main memory is time consuming and also reduces the availablemain memory.

FIG. 4 illustrates a schematic diagram of an operating system 400comprising a kernel 402, a device drivers layer 404, an applicationprogram interface (API) 406 and a library layer 408. The kernel 402provides the core function of the operating system as mentioned withrespect to FIG. 3. Application programs directly or indirectly rely onthese and other capabilities of the kernel and other portions of theoperating system. The device drivers layer 404 contains the devicedrivers necessary to control and communicate with devices. The operatingsystem also provides the interface between the hardware and theapplication programs layer. To facilitate development of applicationprograms, the operating system also includes application programinterfaces (APIs) 406 to interact with application programs. An API is aset of routines that application programs use to access lower levelservices performed by the operating system. The operating systemperforms a number of services for the application programs includingmodule management, inter-process communication (IPC) and scheduling.Another service provided is the dynamic linked libraries (DLL) containedin the library layer 408. The operating system performs modulemanagement by supporting the linking, loading and execution of DLLsavailable in the library layer.

The operating system also organizes the instructions from applicationprograms into chunks called threads. A thread can be thought of as apacket of instructions that can be “chewed” for execution by the CPU.The operating system breaks the operation of multiple applicationprograms into threads for sequential execution thus allowing the CPU tosimultaneously support several application programs known asmulti-tasking. Multi-tasking in one example increases the speed of acomputers operation by allowing various devices to operate withoutidling the CPU. Usually, the CPU executes instructions much more quicklythan data can be read and written into a storage device. Thus, the CPUwould be idle if it had to wait for data to be written or read from astorage device. The use of threads allow the operating system toreassign the CPU whenever a task must be performed for a slow componentof the system. For example, the processing of instructions from a firstapplication program may be suspended whenever data must be read from adisk drive. The CPU may then execute a thread from another applicationprogram while the data is being read, and resume processing of theinstructions from the first application program, once the data has beenread.

The computer using a bus architecture usually has one bus in which theCPU and the various devices communicate through. Thus, the operatingsystem controls a flow of instructions to the CPU from applicationprograms, and temporal suspension of CPU processing of applicationprogram instructions to allow for the I/O communication by variousdevices such as the data transfer from the disk drive to the main memoryvia the DMA controller.

The computer system using an operating system described above has anundesirable lengthy power-up sequence that inconveniences the user andconsumes valuable memory space. A known method uses a faster CPU tospeed up the power-up sequence. However, a faster CPU is expensive andincreases the cost of the computer. The computer system relying on theoperating system is subject to “crashes” perhaps due to a taintedapplication program it had executed, or due to errors resulting fromhandling numerous interrupts and call procedures during multi-tasking.In addition, the operating system is subject to virus attacks that mayrender the computer system inoperational as well as destroying valuabledata files. What is needed is a computer system and method that solvesthese and other shortcomings.

SUMMARY OF THE INVENTION

Embodiments of the present invention provides computer architecture,hardware and method that eliminates a need for an operating system.

In one general aspect, a computer system comprises a central processingunit (CPU), a main memory, a further unit that includes a firstmicrocontroller and a first memory containing a first set ofinstructions configured to cause the microcontroller to manage CPUoperations, and a plurality of trace links connecting the further unitto the CPU and the main memory to facilitate communication between thefurther unit, the CPU and the main memory. Other features include atleast one device, a trace link connecting the device to the furtherunit, and the further unit further includes a second microcontroller anda second memory containing a second set of instructions configured tocause the second microcontroller to manage the device; the further unitfurther includes a third microcontroller and a third memory containing athird set of instructions configured to cause the third microcontrollerto manage memory operations; the further unit further includes a fourthcontroller and a fourth memory containing a fourth set of instructionsconfigured to cause the fourth controller to manage data operations; theplurality of microcontrollers in the further unit are connected togetherto communicate with each other; the further unit includes a cross-barswitch to connect the plurality of microcontrollers; the device includesa fifth microcontroller and a fifth memory containing a fifth set ofinstructions configured to cause the fifth microcontroller to controlthe device operations, the fifth microcontroller in communication withat least the second microcontroller; the fifth set of instructions inthe fifth memory further configured to cause the fifth microcontrollerto test the device and if the device is operational the fifth set ofinstructions is configured to cause the fifth microcontroller to signalat least the second microcontroller to indicate availability of thedevice; the fifth set of instructions in the fifth memory furtherconfigured to cause the fifth microcontroller to signal at least thesecond microcontroller to indicate availability of the device includessending device identification and required resource data; the second setof instructions in the second memory further configured to cause thesecond microcontroller to receive the signal indicating availability ofthe device and allocating available resources to the device.

In another aspect of the invention an apparatus for managing computeroperations comprises a first microcontroller and a first memorycontaining a first set of instructions configured to cause themicrocontroller to manage central processing unit (CPU) operations.

Other features include a second microcontroller and a second memorycontaining a second set of instructions configured to cause the secondmicrocontroller to manage device operations; a third microcontroller anda third memory containing a third set of instructions configured tocause the third microcontroller to manage memory operations; a fourthcontroller and a fourth memory containing a fourth set of instructionsconfigured to cause the fourth controller to manage data operations; theplurality of microcontrollers are connected together to communicate witheach other; a cross-bar switch to connect the plurality ofmicrocontrollers; wherein the memory is a read only memory (ROM);wherein the memory is an erasable programmable ROM (EPROM); wherein thememory is a Flash memory; wherein the microcontrollers are digitalsignal processors (DSPs); wherein the apparatus is contained in asemiconductor chip; a device including a fifth microcontroller and afifth memory containing a fifth set of instructions configured to causethe fifth microcontroller to control the device operations, the fifthmicrocontroller in communication with at least the secondmicrocontroller; the fifth set of instructions in the fifth memoryfurther configured to cause the fifth microcontroller to test the deviceand if the device is operational the fifth set of instructions isconfigured to cause the fifth microcontroller to signal at least thesecond microcontroller to indicate availability of the device; the fifthset of instructions in the fifth memory further configured to cause thefifth microcontroller to signal at least the second microcontroller toindicate availability of the device includes sending deviceidentification and required resource data; the second set ofinstructions in the second memory further configured to cause the secondmicrocontroller to receive the signal indicating availability of thedevice and allocating available resources to the device.

In another aspect of the invention a device for use in a computer systemthat eliminates a need for an operating system comprises devicecircuitry, a first microcontroller and a memory containing a set ofinstructions configured to cause the microcontroller to control devicecircuitry, the instructions further configured to facilitate themicrocontroller to communicate with a second microcontroller thatmanages a central processing unit (CPU) operation.

BRIEF DESCRIPTION OF THE DRAWING

For better understanding of the invention, reference is made to thedrawings that are incorporated herein by reference and in which:

FIG. 1 illustrates a conventional computer system architecture;

FIG. 2 illustrates a conventional hardware platform layer of thecomputer architecture of FIG. 1;

FIG. 3 is a flow diagram of a conventional Basic Input Output System(BIOS) and kernel start-up operation;

FIG. 4 illustrates a conventional operating system;

FIG. 5 illustrates a computer architecture with hardware/firmware layerthat eliminates the need for an operating system;

FIG. 6 is a semiconductor chip used in a computer system without anoperating system in accordance with one embodiment of the invention;

FIG. 7 illustrates a cross-bar switch that connects various Managers inthe chip used in a computer system without an operating system inaccordance with one embodiment of the invention;

FIG. 8 illustrates a mesh link that connects various Managers in thesemiconductor chip used in a computer system without an operating systemin accordance with another embodiment of the invention;

FIG. 9 illustrates Device Manager interfaces in accordance with anembodiment of the invention;

FIG. 10 illustrates Process Manager interfaces in accordance with anembodiment of the invention;

FIG. 11 illustrates Memory Manager interfaces in accordance with anembodiment of the invention;

FIG. 12 illustrates Information Manager interfaces in accordance with anembodiment of the invention;

FIG. 13 is an exemplary layout of a computer motherboard containing thechip used in a computer system without an operating system and tracelinks;

FIG. 14 illustrates smart devices coupled to the is a semiconductor chipused in a 10 computer system without an operating system chip;

FIG. 15 illustrates a register format in a smart device that includes aserial identification and resource data;

FIG. 16 and FIG. 17 illustrate a power-up sequence in accordance with anembodiment of the invention;

FIG. 18 and FIG. 19 illustrate a sequence for running program/softwareapplications in accordance with an embodiment of the invention;

FIG. 20 and FIG. 21 illustrate a sequence for producing output inaccordance with an embodiment of the invention;

FIG. 22 and FIG. 23 illustrate a sequence for managing files inaccordance with an embodiment of the invention; and

FIG. 24 and FIG. 25 illustrate in general combined Manager interfacesand interactions to perform computer operations in accordance with anembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to hardware/firmware layer in a computer systemthat eliminates a need for an operating system. In one aspect of theinvention, the hardware/firmware layer comprises a Device Manager, anInformation Manager, a Memory Manager, and a Process Manager, which maybe contained in one or more semiconductor chips. Each of the Managerscomprises a microcontroller associated with firmware embedded in ROM orFlash memory that contains instruction sets that cause themicrocontroller to provide a designated task of device management,information management, memory management and process management. Thesemiconductor chip or chip sets, when incorporated into the computermotherboard allows the computer hardware to operate without an operatingsystem. In another aspect of the invention, devices such as disk drives,modem, printer, video monitor, connected to the computer system are“smart devices,” wherein each device has a device microcontroller andembedded device drivers in a ROM or Flash memory. The is a semiconductorchip used in a computer system without an operating system does not needto search for available devices, provide diagnostic tests or obtaindevice drivers to communicate with the devices. Instead the devicemicrocontroller uses the embedded device driver to perform configurationand self diagnostic test autonomously as well as operations of thedevice. If the device is operational, the device microcontroller sendsan identification signal that includes resource requirements to thesemiconductor chip used in a computer system without an operating systemchip via trace links on the motherboard to indicate availability of thedevice.

FIG. 5 is a high-level layer diagram of computer architecture 500containing a hardware/firmware layer 504 that eliminates a need of anoperating system in accordance with an embodiment of the invention. Thearchitecture also comprises a hardware platform layer 502 and anapplication programs layer 506. The hardware platform layer 502 issimilar to a conventional hardware platform layer shown in FIG. 2.However, as will be apparent with respect to FIG. 13, modifications aremade to the hardware platform layer to allow for the various hardwarecomponents and devices such as disk drives, modems, printer, videomonitor to interact with the hardware/firmware layer 604. Theapplication programs layer 506 is similar to the conventionalapplication programs layer shown in FIG. 1 and may include applicationprograms such as word processor, database, spread sheet, browser and soforth.

The hardware/firmware layer 504 provides the services previouslyperformed by an operating system kernel, discussed above. In oneembodiment illustrated in FIG. 6, the hardware/firmware layer 504 takesthe embodiment of an integrated semiconductor chip or chip set 600inserted into the hardware platform. The chip used in the computersystem without an operating system interacts with the CPU and variouscomponents in the hardware platform layer including input devices 650,output devices 660 and permanent storage devices 670. According to theembodiment, the chip 600 comprises four microcontrollers, preferablydigital signal processors (DSPs) 612, 622, 632, 642. Each DSP isassociated embedded firmware that contains one of four routines; adevice management routine 614, a process management routine 624, amemory management routine 634 and an information management routine 644.These routines are within the knowledge of those skilled in the art ofoperating system designs. The firmware may be embedded in ROM, erasableprogrammable ROM (EPROM), Flash memory and the like. A microcontrollerand an associated firmware forms one of a Device Manager 610, anInformation Manager 640, a Memory Manager 630 and a Process Manager 620,as shown in FIG. 6. The Device Manager 610 is linked directly to and hasaccess to the Input/Output (I/O) devices 650, 660 and permanent storagedevices 670. The Information Manager 640 and the Device Manager 610 arelinked directly to and have access to the permanent storage devices 670.The Memory Manager 630 is directly linked to and has access to the mainmemory 206. The Process Manager 620 is directly linked to and has accessto the CPU 202. The Managers 610, 620, 630, 640 are connected togetherso that a Manager can communicate with another Manager or Managers.Various methods of connections may be used such as a cross-bar switch750 shown in FIG. 7 or a mesh connection shown in FIG. 8. Thearchitecture using the chip in the a computer system without anoperating system is inherently robust because each Manager operatesindependently and is interfaced only with those components and devicesapplicable to its operation. In addition, interaction with thecomponents and devices is performed at hardware level without anintervening software level such as an operating system that is subjectto crashes. Further descriptions of the Managers are now given.

With reference to FIG. 6 and FIG. 9, the Device Manager 610 identifiesall devices 650, 660, 670 connected to the computer system andestablishes their means of connection, control unit functionality, anddevice capacity and capability as will be apparent with respect to FIG.14. The device management routine 614 provides the instructions thatallow the Device Manager 610 to act as an I/O scheduler by allocatingdevices 650, 660, 670 to tasks, initiating operations by the device andreclaiming the device on task completion. The user's interaction withthe computer's resources is via requests submitted to Device Manager 610from input devices 650 such as a mouse or a keyboard supported by agraphic user interface (GUI) provided via Device Manager 610 to theuser's screen.

With reference to FIG. 6 and FIG. 10, the Process Manager 620 acts onprocess requests submitted via Device Manager 610. Using theinstructions provided by the process management routine 624, the ProcessManager 620 directly allocates CPU 202 resource to each request based onits needs including the allocation of registers within the CPU 202 andmain memory 206. The Process Manager 620 will also request the DeviceManager 610 to process relevant data transfer to main memory 206 fromthe permanent storage device 670. Process Manager 620 also provides acontinuous tracking of the CPU 202 capacity and the status of processesand will reclaim the CPU 202 for new activities as each processterminates or exceeds allocated resources.

With reference to FIG. 6 and FIG. 11, The memory management routine 634provides the instructions for the Memory Manager 630 to allocate memory206 resources to the Process Manager 620 based on the immediate memoryneeds of the jobs being controlled by Process Manager 620. The MemoryManager 630 also responds to direct requests via Device Manager 610 formemory 206 resource. The Memory Manager 630 constantly tracks the userand associated amount of each element of memory being utilized and ontermination of jobs, reclaims and makes memory resources re-available.Memory Manager 630 logically partitions the memory resource into twoareas. One is reserved for resident applications in use (e.g. Microsoft™Word™) and the other for process requirements (e.g. a datafile beingworked on by Excel™ or a program being developed in C++). Applicationsin use are loaded sequentially into the application memory space. Filesand data only occupy the process memory space when they are beingoperated on and the Memory Manager 630 prioritizes, schedules andmaintains an external queue for memory resource.

With reference to FIG. 6 and FIG. 12, the information management routine644 provides the instructions for the Information Manager 640 to providethe means for the user to make decisions about planned and current useof the computer system's facilities by providing a complete informationresource record and management capability for the entire system. Usinginput from the other Managers and directly from connected permanentstorage devices 670, it maintains a file management record file in themain memory 206. This contains the location, use and size of all files,the status of all files (i.e. open/close, file type, security levels)and the overall capacities and usage levels of memory 206, input devices650, output devices 660 and permanent storage devices 670.

Other aspect of the computer architecture includes a graphic userinterface (GUI) and an applications program interfaces (APIs). The GUIand API may be implemented as software and stored in the permanentstorage device until called by the chip 600 that is used in a computersystem without an operating system. For instance, the graphic userinterface (GUI) may be contained in the permanent storage device untilretrieved by the pertinent Manager during power-up sequence. Designing aGUI is well known in the art and will not be further discussed here.Regarding presently-available application software programs, such asMicrosoft™ Office Suite™, Lotus Notes™, Corel Draw™, Symantec™ Winfax™and ACT™, each of these programs require an associated Operating Systeminterface that is written into the application. Thus, the softwareprogrammed to a particular Operating System type. To accommodate suchpresently available programs within the computer architecture that haseliminated the operating system, a corresponding API to the software isstored in the permanent storage device and is called into main memorywhen the software is operational to act as an interface between theapplication software and the chip 600. Alternatively, the APIs may bestored in a web-site and the pertinent API is called by the chip 600 viathe modem 246 into the main memory 206 when an associated applicationprogram is being loaded into memory 206.

FIG. 13 is a layout of an exemplary computer motherboard 1300 containingthe chip 600 that is used in a computer system without an operatingsystem. The motherboard also includes chip sets C1, C2, C3, C4 thatcontain the various controllers such as the memory controller, directmemory access (DMA) controller, interrupt controller, input/output (I/O)controller, integrated drive electronics (IDE) controller, supportingcircuitry and an array of dynamic random access memories (DRAMs) 1302that constitute the main memory. Also included on the mother board 1300is a CPU slot 1303 that is configured to receive the CPU 202 and variousperipheral device connectors such as keyboard port 1304, UniversalSerial Bus (USB) port 1306, game port 1307, serial port 1308, parallelports 1312, floppy Drive controller (FDC) connector 1314, primary andsecondary IDE connectors 1316 and expansion slots such as PersonalComputer Interface (PCI) bus slots 1318, Industry Standard Architecture(ISA) bus slot 1316, and advanced graphics port (AGP) bus slot 1322. Themotherboard further includes the BIOS ROM 1326 that contains the BIOSincluding Power On Self Test (POST) routine. In one embodiment, the BIOSprovides the services of a conventional POST, configuration of systemlevel devices and controllers such as PO interfaces, keyboardcontroller, video controller, timer, direct memory access (DMA)controller, peripherals interface controller and so forth, and abootstrap to the chip 600. In accordance with an embodiment of theinvention, the peripheral device connectors and the expansion slots areconnected to the respective Manager in the chip 600 via trace links1328. Through the trace links 1328, direct communication occurs betweenthe devices and the chip 600.

Devices are directly connected at a physical level to the Device Manager610 of the chip 600 and device recognition and management is separatedfrom any information, memory or processing functions. The means by whicheach device is made available to the chip 600 is through themicrocontroller with embedded device driver contained within a deviceitself.

A smart device 1400, illustrated in FIG. 14, contains a devicemicrocontroller 1402 and embedded device driver 1404 within the device1400 that allows it to configure and perform self diagnostic test aswell as operations of the device, hence is smart in the sense that itoperates independently without external control source. Smart devicesinclude devices such as disk drives, modem, printer, video monitor andso forth. Smart devices are interfaced with the pertinent Manager in thechip used in the computer system without an operating system to makeavailable the services of the devices. According to one aspect of theinvention, at power-up initialization, individual devicemicrocontrollers 1402 within the devices 1400 are activated, each devicemicrocontroller 1402 having a startup address pointing to the embeddedROM contained in the device 1400. The ROM can contain a device driver1404 that is particular to the device that the device microcontroller1402 uses to configure and perform self diagnostic test. In one aspectof the invention, each device microcontroller 1402 in the one or moredevices 1400 perform the configuration and diagnostics autonomously andsimultaneously or substantially simultaneously. If, after the previousprocedure, the device 1400 is deemed to be operational, the devicemicrocontroller 1412 sends an identification signal 1500, which isstored in registers, such as the one illustrated in FIG. 15, to the chip600 used in a computer system without an operating system via the tracelink 1328 to indicate availability of the device 1400. Theidentification signal 1500 may be a string of data bits transmittedserially or in parallel that comprises of device identification bits1502 and required resource data bits 1504. The signal may conform to theserial identifier and resource data format of the Plug and Play ISASpecification. It should be noted that the signal configuration may bein any format standard established with or by device manufacturers. TheDevice Manager 610, upon receiving the identification signal, recognizesthe presence of the device. Because the Device Manager 610 has access toavailable system resources, the Device Manager 610 identifies theresources required by the device and allocates the appropriate resourcesto the device. Resource allocation is usually performed in a manner thatdoes not conflict with other devices that require system resources. Theresource allocated device is assigned an address that acts as a pointerto the device. It should be noted that because the number of I/O andstorage devices and the ability to communicate with them ispredetermined as a function of the total peripheral device connectors,expansion slots and associated trace links to the chip 600, in oneembodiment, device recognition and logical connectivity can be based ona finite state machine.

As can be seen by reference to FIG. 13, the chip 600 used in a computersystem without an operating system is shown as being directly connectedto the CPU (CPU slot 1303) and the main memory (memory slots 1302). Thusthe CPU 202 and memory 206 (see FIG. 6) can focus entirely on processrequirements and multi-tasking management that are performed by theProcess Manager 620 and the Memory Manager 630 within the chip 600. As aresult, when insufficient memory or CPU capacity is available, then nomore processes are added to the system and the request is rejected atthe input device level rather than causing a potential crash at thesystem level. As a result of separating processing and memory managementfrom other routines, the processing speed is a straightforwardrelationship between the stated CPU 202 capacity, the memory 206capacity and the transfer rate between and amongst the chip 600, the CPU202 and the memory 206. This serves to provide robustness in thecomputer architecture as well as faster interaction between the CPU 202and memory 206 as the CPU 202 need not be diverted to process othermiscellaneous routines.

As there is no resident Operating System in the main memory 204, all ofthe memory capacity is directly available for the user's tasks at hand.The Memory Manager 630 performs the management of the available memorycapacity and queues programs and data awaiting processing externally andensures that sufficient memory is always available to support a processrequest. As a result, it is not necessary to continually swap datafiles, program elements or address map data between storage and memoryto continue satisfying a processing requirement. This serves to operatethe CPU 202 at optimal capacity because the CPU 202 is not diverted tomiscellaneous task of off-loading unnecessary files or program elementsto make space in the memory for the currently executing program orprograms.

The Information Manager 640 maintains an inventory of permanent storageaddresses and transfers files into and out of memory on an “as required”and “on completion” basis. Combined with the Memory Manager 630, featuredescribed above results in high-speed data access at both the processingand file management level and minimizes/optimizes the hard disk memoryutilization.

It should be noted that, because an entire level of software, that isthe operating system, is removed from the computer system, this sectionreduces the risk of the system being open to virus attack. As a resultof the direct physical connection between devices 650, 660, 670, thechip 600, CPU 202 and memory 206, files arriving for processing frompermanent storage devices are not exposed to other software interfaceswhen entering the computer system and therefore avoid potentialcontamination. Crashes caused by contaminated external files entering anI/O device 650, 660 from outside will occur at device level rather thanaffecting the entire system. Because of the modularity of the Managersin the chip used in a computer system without an operating system,security measures can be taken at the Information Manager 640, forinstance, so that contaminated external files or viruses are filteredand does not expose the files or viruses to the entire system.

Another example of security precaution, when an external communicationdevice (e.g. modem or LAN card) is connected to the Device Manager 610,Data Security Inspection (DSI) software embedded in the Device Manager610 inspects the file. If the file is suspect, the Device Manager 610quarantines it in a retention area and flags the file problem to theuser. There is no exposure of the relevant permanent storage device tothe file thus avoiding system corruption.

FIG. 16-25 illustrate the example operations performed by the Managerswithin the chip 600 used in a computer system without an operatingsystem. FIG. 16 and FIG. 17 illustrate a power-up sequence in accordanceto one embodiment of the invention. On power-up, at stage 172, the BIOS1326 (see FIG. 13) is activated to invoke POST routine. In oneembodiment a commercially available BIOS such as those from PhoenixTechnologies, Ltd. is used, however, the bootstrap sequence is modifiedto bootstrap to the chip 600. POST conducts a standard memory check andshadows the BIOS into the main memory 206. In stage 174, the BIOSconfigures the various controllers and bootstrap to the Device Manager610 in the chip 600. In the meantime, at stage 176, various smartdevices such as those described with respect to FIG. 14 and representedby I/O devices 650, 660 and permanent storage devices 670 initiate selftest and configuration and if operational, the smart devices enable anidentification signal to indicate their availability. The Device Manager610 recognizes the existence of each device 650, 660, 670. For devices650, 660, 670 such as a keyboard, mouse or video monitor, the signal isgenerated through the motherboard BIOS ROM 1326 or their built in BIOScommunicates directly to the chip 600. For other devices 650, 660, 670recognition is achieved through electrical connectivity signalled by asignal generator on the device.

At stage 178, the availability, capability and compatibility of eachdevice 650, 660, 670 is enabled. Logical connectivity is based upon thefinite state machine concept. Each device 650, 660, 670 is assigned anaddress in memory that acts as a pointer to the device.

At stage 180, Information Manager 640 loads a file containing therecognized system state on previous shut-down. This contains pointerstowards the record fields for all available programs and data files oneach permanent storage device 670. At stage 182, the Information Manager640 passes control to the Process Manager 620 along with an instructionto load the graphical user interface (GUI) from a predetermined fixeddrive location. Process Manager 620 displays the GUI via the DeviceManager 610 to the screen of the video monitor. The Information Manager640 icon is displayed on the screen along with icons representing dataor program files which the user had screen displayed prior to shut down.The chip 600 used in a computer system without an operating system isnow ready to recognize and act on user requests or other inputs. Aninterrogation of the Information Manager 640 would reveal the GUI,record field file and device record file resident in memory, which wouldindicate the devices connected and their current status.

FIG. 18 and FIG. 19 illustrate an exemplary procedure for runningprogram/software applications. At stage 192, the user inputs thisrequest typically via input device 650 such as mouse and/or keyboard andtheir interface with Device Manager 610. At stage 194, the request issent to Process Manager 620, which in combination with Memory Manager630, identifies the appropriate files from the register in the memory,which identifies if sufficient memory 206 and CPU 202 resource isavailable, allocates it and requests the files from Device Manager 610,at stage 196. At stage 198, Device Manager 610 directs the relevantfiles from the device to memory. At stage 202, program fileidentification occurs between the Process Manager 620 and the MemoryManager 630. At stage 204, the Memory Manager 630 keeps track of thememory management, allocation of memory used by the programs. Theprogram runs until it is complete or exceeds the resource allocated.Storage requirements during the program run are coordinated between theDevice Manager 610 and the Memory Manager 630, at stage 206. In-processfile request, queuing and delivery is coordinated between the ProcessManager 620 and the Memory Manager 630, stage 208. At stage 212, iffurther user input is required, Process Manager 620 requests this of theuser via the Device Manager 610 interface. The Information Manager 640provides the user with a picture of the remaining system resources ifrequired, at stage 214.

FIG. 18 and FIG. 19 also illustrate an exemplary procedure of concurrentprocessing. Inter-process communication and instruction, (e.g. MicrosoftExcel, a spread sheet program that requests the Process Manager 620 torun Microsoft PowerPoint, a presentation program) is handled in asimilar manner. At stage 208, an inter-process request queue is createdon a permanent storage device 670 and these are then scheduled as inputrequests in the above manner. As the management of program takes placeoutside of the CPU 202 and memory 206, the ability to continue to loadand run more and more program is a straightforward function of comparingtheir combined memory 202 and CPU 202 requirement with the programsrequirement. The Process Manager 620 and Memory Managers 630 conductthis task. The Memory Manager 630 also provides the Device Manager 610with the information required to queue data on permanent storage priorto allocation of memory at the time of processing, stage 206. In anoperating systemless approach the criteria for subsequently reclaimingthe processor resource is pre-defined prior to its allocation to aparticular processing requirement. This requirement is either completedand the next process is loaded or it exceeds its pre-allocated resourceand is interrupted. Information Manager 640 provides the user with acontinuous status indication and allows advance recognition of potentialsystem overload. In addition, an inadvertent attempt to overload thesystem will simply be met with a message indicating that the processcannot be performed. As the CPU 202 and memory 206 are not engaged atthis point, there is no danger of a system crash.

FIG. 20 and FIG. 21 illustrate an exemplary procedure for producingoutput (e.g. Printing Information). At stage 222, the application (e.g.Microsoft Word) generates a print file that is sent by Device Manager610 directly to the “Queue station” application. This is standardsoftware operating on a first in first out (FIFO) principle. Thisapplication is either resident on the hard disk managed directly by anprinter controller via the Device Manager 610 connection or ideally,embedded in the printer controller itself. At stage 224, the first jobin the queue application is placed in a memory location reserved forprint jobs on receipt of a signal from an output device 660 such as aprinter that a job is underway. When the printer releases the first jobwith a signal to Device Manager 610, at stage 226, the next job isloaded into the printer memory, at stage 228. In the event of a fault,the “live job” is simply released from the printer memory. Anydifficulties are confined to the printer and there is no danger of asystem crash. This same procedure is also of course applicable to anetworked printer or other networked device with minimum modification.The queue application routes the data to the IP address of the devicethrough either the LAN connection or network card which would have beenidentified at start-up. Again, any problems are confined to theparticular device and do not impact the CPU 202 or other programmes orfiles in memory 206.

FIG. 22 and FIG. 23 illustrate an exemplary procedure for managingfiles. At stage 232, via the GUI, the user interrogates InformationManager 640, which retains information about files resident both onmemory 206 and on permanent storage 670. Files contain two elements, adescriptor field containing all relevant information about the file(e.g. whether it is a data or programme file, or whether it is a readonly or fully accessible file) and the actual data field. Only thedescriptor fields and not the actual data are stored in memory for theuse of Information Manager 640. These can be changed directly via DeviceManager 610 for secondary storage based files. As a consequence filesecurity levels or type changes or descriptions are directly alteredwithout consuming CPU 202 resource and without accessing the entire fileand consuming memory 206 resource. At stage 234, a user requested filetransfer is effected following a user request (using e.g. a mouse) toDevice Manager 610. This simply passes the file from one storage device670 to another, at stage 236, and advises Information Manager 640 of thechange in device associated with the file. No interaction with the CPU202 or memory 206 is required. For a user saving a file in use by anapplication (e.g. an Excel file in use resident in memory), the file issent using Memory Manager 630 via Device Manager 610 to the relevantdevice similar to a normal output request. This process, including anyqueuing requirement is dealt with in a manner similar to the printingprocess above.

FIG. 24 and FIG. 25 illustrate in general combined Manager interfacesand interaction of the pertinent Managers to perform various computersystem operations. At function 1, a user process request such as toretrieve program, data or file invokes the Device Manager 610. Atfunction 2, output requests, such as print jobs or sending fax via amodem, causes the Device Manager 610 to interact with the pertinentoutput device 660. A user request such as a file transfer from thepermanent storage device 670 invokes the Device Manager 610 to accesspermanent storage device 670 and retrieve the file. At function 4 inconjunction with function 5, a user request for information such as fileinformation, first invokes the Device Manager 610 that, in turn,determines the nature of the request and passes the request to theInformation Manager 640. The Information Manager 640 accesses thepermanent storage device that contains the file and retrieves therequested file information. The file information is passed to the DeviceManager 610 that passes the information to the user via an output device660 such as a video monitor. Functions 6-12 pertain to programexecution. A user request to execute a program causes the Device Manager610 to request the Process Manager 620 for a process execution, atfunction 6. At function 7, the Device Manager 610 interacts with theMemory Manager 630 to load the program into memory 206. At functions 8and 9, the Device Manager 610 indicates to the Information Manager 640that a program is to be executed that causes the Information Manager 640to gather process use and process capacity information, and to gathermemory 206 use and memory 202 capacity. At functions 10, the MemoryManager 630 interacts with the Process Manager 620 to provide memoryrequirements and memory space allocation, among others. At function 11,the Process Manager 620 initiates the CPU 202 to begin execution of theprogram while continually controlling and monitoring the CPU 202execution cycles. In the meantime, the Memory Manager 630 continuallycontrols and monitors memory 206 usage and capacity, and memory 206allocation.

Thus, providing an firmware/hardware layer that eliminates the need foran operating system and making minor modification to the computermotherboard provides for a revolutionary new interface at the hardwarelevel between the user, the computer hardware resource and the devices.It satisfies all user requirements traditionally handled by an OperatingSystem in a faster, cheaper, more robust and more straightforwardfashion, eliminating the need for an Operating System. The eliminationof the Operating System also relieves Device Manufacturers andApplication providers from platform dependence, making futuredevelopment more straightforward. For instance, Device Manufacturers mayproduce smart devices that contain a device microcontroller and embeddeddevice drivers that eliminate reliance of the operating system.Application providers may produce their own APIs that optimally runstheir software without concerns of the interface rules set by theoperating system. While various embodiments of the application have beendescribed, it will be apparent to those of ordinary skill in the artthat many more embodiments and implementations are possible within thescope of the invention. Accordingly, the invention is not to berestricted but should be read in light of the attached claims and theirequivalents.

1. A computer system that eliminates a need for an operating systemcomprising: a central processing unit (CPU); a main memory; a furtherunit that includes a first microcontroller and a first memory containinga first set of instructions configured to cause the microcontroller tomanage CPU operations; and a plurality of trace links connecting thefurther unit to the CPU and the main memory to facilitate communicationbetween the further unit, the CPU and the main memory.